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- ItemA low-cost picowatt calorimeter using a flexible printed circuit board(Nature Portfolio, 2025-03-27) Zhu, Hanliang; Zhang, Yue; Wang, Lan; Brodský, Jan; Gablech, Imrich; Feng, Jianguo; Yan, Qi-Long; Yang, Shujie; Lee, Luke P.; Neužil, PavelCalorimetry is crucial in biology, chemistry, physics, and pharmaceutical research, enabling the detection of heat changes at nanowatt and picowatt levels. However, traditional calorimetry systems are often limited by high costs and complex fabrication processes. Here, we reduce the cost and fabrication complexity of microcalorimeters by utilizing widely available flexible printed circuit manufacturing processes. This device achieves temperature and power resolutions of 6 K and 654pW in vacuum. Its feasibility is validated across a wide range of measurements, including salt crystallization, protein crystallization, and cellular metabolism. Our concept enhances the accessibility of microcalorimeters for high-resolution thermal analysis, which is challenging for conventional calorimeters.
- Item0.5-V High-Order Universal Filter for Bio-Signal Processing Applications(MDPI, 2025-04-03) Kumngern, Montree; Khateb, Fabian; Kulej, Tomasz; Lerkvaranyu, SomkiatIn this paper, a novel multiple-input operational transconductance amplifier (MI-OTA) is proposed. The MI-OTA can be obtained by using the multiple-input bulk-driven MOS transistor (MIBD MOST) technique. The circuit structure is simple, can operate with a supply voltage of 0.5 V, and consumes 937 pW at a current setting of 625 pA. The proposed MI-OTA was used to implement a high-order multiple-input voltage-mode universal filter. The proposed filter can provide non-inverting and inverting low-pass, high-pass, band-pass, band-stop, and all-pass transfer functions to the same topology. In addition, it has a high input impedance and does not need any inverted input signals, so there is no additional buffering circuit. The proposed filter can be used for biological signal processing. The proposed MI-OTA and the second-order universal filter were simulated in Cadence using CMOS process parameters of 0.18 mu m from TSMC to verify the functionality and performance of the new structures.
- ItemNovel Multiple-Input Single-Output Shadow Filter with Improved Passband Gain Using Multiple-Input Multiple-Output DDTAs(MDPI, 2025-03-31) Kumngern, Montree; Khateb, Fabian; Kulej, TomaszThis paper presents a multiple-input single-output (MISO) shadow filter implemented using multiple-input differential difference transconductance amplifiers (MI-DDTAs). The MI-DDTA's multiple inputs are realized through the multiple-input bulk-driven MOS transistor (MI-BD MOST) technique. Leveraging the multiple-input capability of the DDTA, various filter responses-low-pass filter (LPF), high-pass filter (HPF), band-pass filter (BPF), band-stop filter (BSF), and all-pass filter (APF)-can be efficiently achieved by appropriately configuring the input signals. The natural frequency and quality factor of the shadow filter can be independently tuned using external amplifiers. Unlike conventional shadow filters, where adjusting the quality factor or natural frequency impacts the passband gain, this design ensures a constant unity passband gain. The MI-DDTA operates at a supply voltage of 0.5 V and consumes 385.8 nW of power for setting current Iset = 14 nA. The proposed MI-DDTA and shadow filter are designed and validated through simulations in the Cadence design environment, using a 0.18 mu m CMOS process provided by TSMC (Taiwan Semiconductor Manufacturing Company Limited).
- ItemA new approach to measuring the temperature fields in reflow ovens(Sciendo, 2025-04-10) Hurban, Milan; Szendiuch, IvanElectronics play an increasingly significant role in our lives. Consequently, the demand for both production volume and quality in electronics is continuously rising. Conveyor reflow ovens are the most widely used technology for soldering electronic assemblies onto printed circuit boards. The implementation of these ovens directly affects the quality of solder joints and, most importantly, the reliability of manufactured electronic assemblies, which are present in virtually all aspects of daily life. The solder joint is formed by the reflow of the solder alloy and is defined by the thermal profile, which represents temperature over time. The most common heating method relies on forced hot air convection, where the printed circuit board with mounted components moves through the oven. One of the key design requirements for these ovens is maintaining a consistent hermal profile to achieve a homogeneous temperature field across the reflow zones. To assess this condition, it is essential to measure convection under operating conditions. A new method for measuring the temperature field directly within the conveyor oven has been developed and experimentally verified during production.
- ItemDesign, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices(Springer Nature, 2025-04-27) Kubánek, David; Shadrin, Aleksandr; Šeda, Pavel; Dvořák, Jan; Jeřábek, Jan; Kledrowetz, Vilém; Christie, Cole; Freeborn, Todd; Ushakov, Peter A.The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.