Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

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dc.contributor.authorKubánek, Davidcs
dc.contributor.authorShadrin, Aleksandrcs
dc.contributor.authorŠeda, Pavelcs
dc.contributor.authorDvořák, Jancs
dc.contributor.authorJeřábek, Jancs
dc.contributor.authorKledrowetz, Vilémcs
dc.contributor.authorChristie, Colecs
dc.contributor.authorFreeborn, Toddcs
dc.contributor.authorUshakov, Peter A.cs
dc.coverage.issue4cs
dc.coverage.volume15cs
dc.date.accessioned2025-05-26T12:56:05Z
dc.date.available2025-05-26T12:56:05Z
dc.date.issued2025-04-27cs
dc.description.abstractThe article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.en
dc.formattextcs
dc.format.extent18cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationScientific Reports. 2025, vol. 15, issue 4, 18 p.en
dc.identifier.doi10.1038/s41598-025-96539-wcs
dc.identifier.issn2045-2322cs
dc.identifier.orcid0000-0002-0346-0761cs
dc.identifier.orcid0000-0002-6689-1980cs
dc.identifier.orcid0009-0004-3915-9825cs
dc.identifier.orcid0000-0001-9487-5024cs
dc.identifier.orcid0000-0002-6720-1224cs
dc.identifier.other197765cs
dc.identifier.researcheridE-3392-2018cs
dc.identifier.researcheridAAY-3211-2021cs
dc.identifier.researcheridP-7120-2017cs
dc.identifier.researcheridE-3929-2018cs
dc.identifier.researcheridA-1777-2017cs
dc.identifier.scopus8659506800cs
dc.identifier.scopus56955391700cs
dc.identifier.scopus57188853049cs
dc.identifier.scopus23011945600cs
dc.identifier.scopus37461587200cs
dc.identifier.urihttps://hdl.handle.net/11012/251028
dc.language.isoencs
dc.publisherSpringer Naturecs
dc.relation.ispartofScientific Reportscs
dc.relation.urihttps://link.springer.com/article/10.1038/s41598-025-96539-wcs
dc.rightsCreative Commons Attribution-NonCommercial-NoDerivatives 4.0 Internationalcs
dc.rights.accessopenAccesscs
dc.rights.sherpahttp://www.sherpa.ac.uk/romeo/issn/2045-2322/cs
dc.rights.urihttp://creativecommons.org/licenses/by-nc-nd/4.0/cs
dc.subjectdistributed elementen
dc.subjectfractional-order elementen
dc.subjectfractoren
dc.subjectgenetic algorithmen
dc.subjectMOS transistoren
dc.titleDesign, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devicesen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.grantNumberinfo:eu-repo/grantAgreement/GA0/GA/GA23-06070Scs
sync.item.dbidVAV-197765en
sync.item.dbtypeVAVen
sync.item.insts2025.05.26 14:56:05en
sync.item.modts2025.05.26 14:33:12en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav telekomunikacícs
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav mikroelektronikycs
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