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Novel Hybrid UNet++ and LSTM Model for Enhanced Attack Detection and Classification in IoMT Traffic
(IEEE, 2025-03-24) Mezina, Anzhelika; Nurmi, Jari; Ometov, Aleksandr
The Internet of Medical Things (IoMT) transforms healthcare by allowing real-time monitoring, diagnosis, and treatment using interconnected medical devices and sensors. However, the rapid growth of IoMT brings significant security and privacy challenges due to its critical vulnerability to cyber-attacks. This paper introduces a novel deep learning approach designed to analyze IoMT traffic and identify malicious activities. By leveraging the CIC IoMT dataset, we improved an existing neural network model to improve prediction accuracy. Our approach combines UNet++ and Long Short-Term Memory (LSTM) models to extract network traffic features effectively. Experimental results show that the proposed model outperforms traditional algorithms, achieving an accuracy of 99.92% in anomaly detection and 87.96% in attack categorization. Finally, we highlight the main limitations as well as possibilities for real-world implementation of the approach.
Efficient unified architecture for post-quantum cryptography: combining Dilithium and Kyber
(PeerJ, 2025-03-28) Dobiáš, Patrik; Malina, Lukáš; Hajný, Jan
As the ongoing standardization process of post-quantum schemes yields initial outcomes, it becomes increasingly important to not only optimize standalone implementations but also explore the potential of combining multiple schemes into a single, unified architecture. In this paper, we investigate the combination of two NIST-selected schemes: the Dilithium digital signature scheme and the Kyber key encapsulation mechanism. We propose a novel set of optimization techniques for a unified hardware implementation of these leading post-quantum schemes, achieving a balanced approach between area efficiency and high performance. Our design demonstrates superior resource efficiency and performance compared to the previous unified architecture by Aikata et al., also achieving results that are better than or comparable to those of standalone implementations. The efficient and combined implementation of lattice-based digital signatures and key establishment methods can be deployed for establishing secure sessions in high-speed communication networks at servers and gateways. Moreover, the unique and compact design that requires small hardware resources can be directly used in small and cost-effective Field Programmable Gate Array (FPGA) platforms that can be used as security co-processors for embedded devices and in the Internet of Things.
Advancing Perimeter Security: Integrating DAS and CNN for Object Classification in Fiber Vicinity
(IEEE, 2025-04-08) Tomašov, Adrián; Záviška, Pavel; Dejdar, Petr; Klíčník, Ondřej; Da Ros, Francesco; Horváth, Tomáš; Münster, Petr
This paper presents an advanced perimeter protection system that integrates phase-sensitive Optical Time-Domain Reflectometry ( -OTDR) with Convolutional Neural Networks (CNNs) for real-time event classification near optical fibers. The proposed approach enhances traditional security methods by providing robust monitoring in challenging environments, such as low visibility and large-scale areas. We evaluated multiple signal preprocessing techniques, including Fast Fourier Transform (FFT), Redundant Discrete Fourier Transform (RDFT), Discrete Wavelet Transform (DWT), and Mel-Frequency Cepstral Coefficients (MFCC), to optimize classification accuracy and computational efficiency. While MFCC achieved the highest accuracy (85.61%), RDFT provided the best balance between performance (85.47%) and real-time feasibility, making it the preferred method for deployment. The system successfully differentiates events such as vehicle movement, fence manipulation, and construction work, while anomaly detection capabilities further enhance security by identifying irregular activities with minimal error. These findings demonstrate the potential of integrating fiber-optic sensing with deep learning to develop scalable, real-time perimeter protection solutions for critical infrastructure, border surveillance, and urban security.
ML-Aided Dynamic BSR Periodicity Adjustment for Enhanced UL Scheduling in Cellular Systems
(IEEE, 2025-04-15) Chukhno, Nadezhda V.; Saafi, Salwa; Andreev, Sergey
Contemporary research has revealed a limitation in the Uplink (UL) Buffer Status Report (BSR) scheduling procedure - its reliance on outdated information. In addition, a significant limitation in current BSR implementations lies in their inflexibility. The 3rd Generation Partnership Project (3GPP) specifications constrain BSR periodicities to certain quantized values based on Quality of Service (QoS) requirements for various applications. For instance, applications demanding low latency may require very small BSR periodicities, resulting in substantial overhead due to frequent BSR reports. This may result in the wastage of network resources in case of a low BSR periodicity setting. Alternatively, a high BSR periodicity setting may lead packets to wait more at the user buffer and thus result in higher packet latencies. To address these limitations, we propose a framework that predicts time intervals between packet arrivals and subsequently adjusts the BSR periodicity according to the predicted traffic arrivals. The simulation results demonstrate that the proposed Machine Learning (ML)-aided BSR reporting provides flexibility in BSR periodicity adapted to the intensity of traffic arrival and converges to optimal periodicity depending on the mean traffic arrival rate.
Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices
(Springer Nature, 2025-04-27) Kubánek, David; Shadrin, Aleksandr; Šeda, Pavel; Dvořák, Jan; Jeřábek, Jan; Kledrowetz, Vilém; Christie, Cole; Freeborn, Todd; Ushakov, Peter A.
The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

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