Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Kubánek, David; Shadrin, Aleksandr; Šeda, Pavel; Dvořák, Jan; Jeřábek, Jan; Kledrowetz, Vilém; Christie, Cole; Freeborn, Todd; Ushakov, Peter A.

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Files

s4159802596539w.pdf(3.42 MB)

Date

2025-04-27

Authors

Kubánek, David

Shadrin, Aleksandr

Šeda, Pavel

Dvořák, Jan

Jeřábek, Jan

Kledrowetz, Vilém

Christie, Cole

Freeborn, Todd

Ushakov, Peter A.

ORCID

Publisher

Springer Nature

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Abstract

The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

Keywords

distributed element, fractional-order element, fractor, genetic algorithm, MOS transistor

Citation

Scientific Reports. 2025, vol. 15, issue 4, 18 p.
https://link.springer.com/article/10.1038/s41598-025-96539-w

Document type

Peer-reviewed

Document version

Published version

Language of document

en

Document licence

Creative Commons Attribution-NonCommercial-NoDerivatives 4.0 International
http://creativecommons.org/licenses/by-nc-nd/4.0/