Current–Mode Fractional–Order Electronically Controllable Integrator Design

Loading...
Thumbnail Image

Authors

Langhammer, Lukáš
Šotner, Roman
Dvořák, Jan
Sládok, Ondřej
Jeřábek, Jan
Bertsias, Panagiotis

Advisor

Referee

Mark

Journal Title

Journal ISSN

Volume Title

Publisher

IEEE
Altmetrics

Abstract

This contribution presents a design of a current–mode fractional–order electronically controllable integrator which can be used as a building block for a design of fractional–order (FO) circuits. The design is based on a 2nd–order Follow–the–Leader–Feedback topology which is suitably approximated to operate as an integrator of a fractional order. The topology is based on Operational Transconductance Amplifiers (OTAs), Adjustable Current Amplifiers (ACAs) and Current Follower (CF). The proposed structure offers the ability of the electronic control of its fractional order and also the electronic control of the frequency band. Simulations in Cadence IC6 (spectre) and more importantly experimental measurements were carried out to support the proposal. If wider bandwidth where the approximation is valid is required, a higher order structure must be used as also shown in this paper by utilization of a 4th–order FLF topology.
This contribution presents a design of a current–mode fractional–order electronically controllable integrator which can be used as a building block for a design of fractional–order (FO) circuits. The design is based on a 2nd–order Follow–the–Leader–Feedback topology which is suitably approximated to operate as an integrator of a fractional order. The topology is based on Operational Transconductance Amplifiers (OTAs), Adjustable Current Amplifiers (ACAs) and Current Follower (CF). The proposed structure offers the ability of the electronic control of its fractional order and also the electronic control of the frequency band. Simulations in Cadence IC6 (spectre) and more importantly experimental measurements were carried out to support the proposal. If wider bandwidth where the approximation is valid is required, a higher order structure must be used as also shown in this paper by utilization of a 4th–order FLF topology.

Description

Citation

Proceedings of the 2020 IEEE International Conference on Electronics Circuits and Systems (ICECS). 2020, p. 1-4.
https://ieeexplore.ieee.org/document/9294923

Document type

Peer-reviewed

Document version

Accepted version

Date of access to the full text

Language of document

en

Study field

Comittee

Date of acceptance

Defence

Result of defence

Endorsement

Review

Supplemented By

Referenced By

Citace PRO