Comparative Study of Op-Amp-based Integrators Suitable for Fractional-Order Controller Design
dc.contributor.author | Herencsár, Norbert | cs |
dc.contributor.author | Kartci, Aslihan | cs |
dc.contributor.author | Yildiz, Hacer A. | cs |
dc.contributor.author | Šotner, Roman | cs |
dc.contributor.author | Dvořák, Jan | cs |
dc.contributor.author | Kubánek, David | cs |
dc.contributor.author | Jeřábek, Jan | cs |
dc.contributor.author | Koton, Jaroslav | cs |
dc.date.issued | 2019-07-01 | cs |
dc.description.abstract | In this paper, a fractional-order capacitor (FOC) of an order = 0.89 (i.e. constant phase angle –80.1 degree) was emulated via Valsa RC network with five branches. The network component values were optimized using modified least squares quadratic method in a wide frequency range of 100 mHz–1 kHz (i.e. 4 decades) and maximum relative phase error 0.78% was obtained. The design specification corresponds to a speed control system of an armature controlled DC motor, which is often used in control theory. Overall performance evaluation shows the product of evaluated key features (e.g. phase angle deviation and absolute values of relative phase, impedance, and pseudocapacitance errors) for the optimized FOC is 13.3% less than the one obtained via Valsa approximation. The behavior of Op-Amp-based non-inverting configurations of analogue fractional-order integral operator s– employing the optimized FOC, where 0 < < 1, is compared. The behavior of studied integrator circuits is confirmed by SPICE simulations using the readily available Texas Instruments TL072 low-noise Op-Amp macromodel, which is commonly used in electronics. | en |
dc.format | text | cs |
dc.format.extent | 740-743 | cs |
dc.format.mimetype | application/pdf | cs |
dc.identifier.citation | Proceedings of the 2019 42nd International Conference on Telecommunications and Signal Processing (TSP), Budapest, Hungary. 2019, p. 740-743. | en |
dc.identifier.doi | 10.1109/TSP.2019.8768843 | cs |
dc.identifier.isbn | 978-1-7281-1864-2 | cs |
dc.identifier.orcid | 0000-0002-9504-2275 | cs |
dc.identifier.orcid | 0000-0001-5690-7574 | cs |
dc.identifier.orcid | 0000-0002-2430-1815 | cs |
dc.identifier.orcid | 0009-0004-3915-9825 | cs |
dc.identifier.orcid | 0000-0002-0346-0761 | cs |
dc.identifier.orcid | 0000-0001-9487-5024 | cs |
dc.identifier.orcid | 0000-0003-4263-5875 | cs |
dc.identifier.other | 157434 | cs |
dc.identifier.researcherid | A-6539-2009 | cs |
dc.identifier.researcherid | E-2150-2018 | cs |
dc.identifier.researcherid | G-4209-2017 | cs |
dc.identifier.researcherid | P-7120-2017 | cs |
dc.identifier.researcherid | E-3392-2018 | cs |
dc.identifier.researcherid | E-3929-2018 | cs |
dc.identifier.researcherid | E-1241-2018 | cs |
dc.identifier.scopus | 23012051100 | cs |
dc.identifier.scopus | 55576535400 | cs |
dc.identifier.scopus | 21834721500 | cs |
dc.identifier.scopus | 57188853049 | cs |
dc.identifier.scopus | 8659506800 | cs |
dc.identifier.scopus | 23011945600 | cs |
dc.identifier.scopus | 15061338400 | cs |
dc.identifier.uri | http://hdl.handle.net/11012/180513 | |
dc.language.iso | en | cs |
dc.publisher | IEEE | cs |
dc.relation.ispartof | Proceedings of the 2019 42nd International Conference on Telecommunications and Signal Processing (TSP), Budapest, Hungary | cs |
dc.relation.uri | https://ieeexplore.ieee.org/document/8768843 | cs |
dc.rights | (C) IEEE | cs |
dc.rights.access | openAccess | cs |
dc.subject | DC motor | en |
dc.subject | fractional calculus | en |
dc.subject | fractional-order capacitor | en |
dc.subject | fractional-order controller | en |
dc.subject | fractional-order integrator | en |
dc.subject | Op-Amp | en |
dc.subject | Valsa RC network | en |
dc.title | Comparative Study of Op-Amp-based Integrators Suitable for Fractional-Order Controller Design | en |
dc.type.driver | conferenceObject | en |
dc.type.status | Peer-reviewed | en |
dc.type.version | acceptedVersion | en |
sync.item.dbid | VAV-157434 | en |
sync.item.dbtype | VAV | en |
sync.item.insts | 2025.02.03 15:41:29 | en |
sync.item.modts | 2025.01.17 16:55:49 | en |
thesis.grantor | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav radioelektroniky | cs |
thesis.grantor | Vysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav telekomunikací | cs |
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