MOSFET-C transimpedance filters with center frequency tunability feature

Abstract

In this paper, seven different MOSFET-C transimpedance filters with their corresponding transfer functions and basic filter specifications, are provided. Presented designs show second-order standard band-pass, low-pass, or high-pass characteristics. Moreover, some filters provide both low-pass and band-pass characteristics. Especially, having a tunability feature makes a design more useful and applicable for various communication and instrumentation systems. The selected filter topology was biased under various biasing conditions to tune central frequency by keeping bandwidth constant. To elaborate the design with different aspects, we checked its small-signal performance by introducing both changing temperature and implementation errors. The theoretical results are in detail verified by numerous simulations using Cadence IC6 Spectre analog design environment. In the design, transistors with 1.8 V supply voltage were used and modelled by the SilTerra Malaysia 180 nm CMOS process parameters. The implemented layout, including metal-insulator-metal on-chip capacitors, occupies an area of 175 mu m x 75 mu m, while the total power consumption of the filter is found to be only 128.86 mu W.In this paper, seven different MOSFET-C transimpedance filters with their corresponding transfer functions and basic filter specifications, are provided. Presented designs show second-order standard band-pass, low-pass, or high-pass characteristics. Moreover, some filters provide both low-pass and band-pass characteristics. Especially, having a tunability feature makes a design more useful and applicable for various communication and instrumentation systems. The selected filter topology was biased under various biasing conditions to tune central frequency by keeping bandwidth constant. To elaborate the design with different aspects, we checked its small-signal performance by introducing both changing temperature and implementation errors. The theoretical results are in detail verified by numerous simulations using Cadence IC6 Spectre analog design environment. In the design, transistors with 1.8 V supply voltage were used and modelled by the SilTerra Malaysia 180 nm CMOS process parameters. The implemented layout, including metal-insulator-metal on-chip capacitors, occupies an area of 175 mu m x 75 mu m, while the total power consumption of the filter is found to be only 128.86 mu W.