A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

Gonzalez-Diaz, Victor R.; Munoz-Pacheco, Jesus M.; Espinosa-Flores-Verdad, Guillermo; Sanchez-Gaspariano, Luis A.

A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

dc.contributor.author	Gonzalez-Diaz, Victor R.
dc.contributor.author	Munoz-Pacheco, Jesus M.
dc.contributor.author	Espinosa-Flores-Verdad, Guillermo
dc.contributor.author	Sanchez-Gaspariano, Luis A.
dc.coverage.issue	1	cs
dc.coverage.volume	25	cs
dc.date.accessioned	2016-04-20T06:25:35Z
dc.date.available	2016-04-20T06:25:35Z
dc.date.issued	2016-04	cs
dc.description.abstract	This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthesizer simulation is compared with state of the art Verilog-A descriptions showing a reduction of nearly 20 times. In addition, experimental results of a fractional frequency synthesizer are compared to the simulation results to validate the proposed model.	en
dc.format	text	cs
dc.format.extent	89-97	cs
dc.format.mimetype	application/pdf	en
dc.identifier.citation	Radioengineering. 2016 vol. 25, č. 1, s. 89-97. ISSN 1210-2512	cs
dc.identifier.doi	10.13164/re.2016.0089	en
dc.identifier.issn	1210-2512
dc.identifier.uri	http://hdl.handle.net/11012/57914
dc.language.iso	en	cs
dc.publisher	Společnost pro radioelektronické inženýrství	cs
dc.relation.ispartof	Radioengineering	cs
dc.relation.uri	http://www.radioeng.cz/fulltexts/2016/16_01_0114_0123.pdf	cs
dc.rights	Creative Commons Attribution 3.0 Unported License	en
dc.rights.access	openAccess	en
dc.rights.uri	http://creativecommons.org/licenses/by/3.0/	en
dc.subject	Frequency Synthesizers	en
dc.subject	Fractional	en
dc.subject	Modeling	en
dc.subject	Sigma-Delta	en
dc.subject	Phase Noise	en
dc.subject	Verilog-A	en
dc.title	A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment	en
dc.type.driver	article	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en
eprints.affiliatedInstitution.faculty	Fakulta eletrotechniky a komunikačních technologií	cs

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