A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

Gonzalez-Diaz, Victor R.; Munoz-Pacheco, Jesus M.; Espinosa-Flores-Verdad, Guillermo; Sanchez-Gaspariano, Luis A.

A Verilog-A Based Fractional Frequency Synthesizer Model for Fast and Accurate Noise Assessment

Files

16_01_0089_0097.pdf(5.24 MB)

Date

2016-04

Authors

Gonzalez-Diaz, Victor R.

Munoz-Pacheco, Jesus M.

Espinosa-Flores-Verdad, Guillermo

Sanchez-Gaspariano, Luis A.

Publisher

Společnost pro radioelektronické inženýrství

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Abstract

This paper presents a new strategy to simulate fractional frequency synthesizer behavioral models with better performance and reduced simulation time. The models are described in Verilog-A with accurate phase noise predictions and they are based on a time jitter to power spectral density transformation of the principal noise sources in a synthesizer. The results of a fractional frequency synthesizer simulation is compared with state of the art Verilog-A descriptions showing a reduction of nearly 20 times. In addition, experimental results of a fractional frequency synthesizer are compared to the simulation results to validate the proposed model.

Keywords

Frequency Synthesizers, Fractional, Modeling, Sigma-Delta, Phase Noise, Verilog-A

Citation

Radioengineering. 2016 vol. 25, č. 1, s. 89-97. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2016/16_01_0114_0123.pdf

Document type

Peer-reviewed

Document version

Published version

Language of document

en

Document licence

Creative Commons Attribution 3.0 Unported License
http://creativecommons.org/licenses/by/3.0/