Low Latency SC Decoder Architecture for Interleaved Polar Codes

Abstract

Interleaved polar (I-Polar) codes, a new facet of polar codes to achieve better channel capacity, is designed by placing the interleaver and deinterleaver blocks midway between the stages of the polar codes. Low latency hardware optimization makes their implementation even more suitable for ultra-reliable low latency applications. This study proposes an optimal hardware design for low latency interleaved polar codes by reframing the last stage of the interleaved successive cancellation decoder. A high-speed adder-subtractor is used to reduce the latency further, thus increasing the speed of operation. Interleaving data in the proposed polar codes augment BER performance compared to conventional (n, k) polar codes. The proposed I-Polar codes are synthesized using Synopsys design compiler (SDC) in CMOS 65-nm technology. Results show that the latency is reduced by 50.5% on average compared to the conventional polar codes as high-speed adder and merged processing elements are used. Moreover, the average gate count and power are reduced by 14% and 40.56%, respectively.