High-Matching Current-Starved Inverter for Two-Dimensional Vernier Time-to-Digital Converter

Abstract

This paper proposes a novel improved CurrentStarved Inverter (CS-INV) for application in a ring oscillator, integral to a 2D Vernier time to digital converter. Through the comparative analysis of two prevalent CS-INV topologies, we introduce a novel topology aimed at minimizing delay variation within the ring oscillator (caused by mismatches between CSINVs in the ring oscillator), which is essential for ensuring good Integral and Differential Nonlinearity. The primary objectives were to achieve minimal delay variation and to reduce current consumption, while ensuring functionality at the slowest PVT corners. The ring oscillator operates at 640 MHz and comprises 26 CS-INVs. The design, implemented in 65 nm CMOS technology, demonstrated a delay matching variation of 2.03 ps with a current consumption of 384 mu A. The performance metrics were substantiated through simulations using a high-sigma verification tool.

This paper proposes a novel improved CurrentStarved Inverter (CS-INV) for application in a ring oscillator, integral to a 2D Vernier time to digital converter. Through the comparative analysis of two prevalent CS-INV topologies, we introduce a novel topology aimed at minimizing delay variation within the ring oscillator (caused by mismatches between CSINVs in the ring oscillator), which is essential for ensuring good Integral and Differential Nonlinearity. The primary objectives were to achieve minimal delay variation and to reduce current consumption, while ensuring functionality at the slowest PVT corners. The ring oscillator operates at 640 MHz and comprises 26 CS-INVs. The design, implemented in 65 nm CMOS technology, demonstrated a delay matching variation of 2.03 ps with a current consumption of 384 mu A. The performance metrics were substantiated through simulations using a high-sigma verification tool.