Capacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Technique

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dc.contributor.authorŠotner, Romancs
dc.contributor.authorJeřábek, Jancs
dc.contributor.authorPolák, Ladislavcs
dc.contributor.authorPetržela, Jiřícs
dc.coverage.issue1cs
dc.coverage.volume8cs
dc.date.issued2020-08-05cs
dc.description.abstractThis paper presents a new concept of a capacitance multiplier using the topology of differential voltage buffer and current conveyor, where the capacitor is connected to the current input terminal. The presented topology overcomes the typical issue known from similar solutions, i.e. creation of an undesired lossy character of the impedance plot. The added feedback path in the structure serves for minimization of the serial parasitic resistance of the current input terminal as well as the output resistance of differential voltage buffer. The electronic driving of the current and voltage internal gains of the active elements allows the adjustment of the capacitance multiplication factor as well as readjustment of the overall capacitance structure between the lossy and lossless modes of operation. The adjustment of the multiplication factor intentionally targets low ranges of gains. Despite that the multiplication factor equals or is less than 1, the range of adjustability is very wide. Simple modifications of the proposed concept leading to the differential-mode operation and enhancement of the multiplication factor are shown and explored. They were experimentally tested in more than 2 decades, from 0.03 to 5.8 nF, and controlled by single DC voltage from 0.1 to 1.0 V. The outputs of experimental measurements meet with the PSpice simulations and confirm the design validity.en
dc.formattextcs
dc.format.extent144382-144392cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationIEEE Access. 2020, vol. 8, issue 1, p. 144382-144392.en
dc.identifier.doi10.1109/ACCESS.2020.3014388cs
dc.identifier.issn2169-3536cs
dc.identifier.orcid0000-0002-2430-1815cs
dc.identifier.orcid0000-0001-9487-5024cs
dc.identifier.orcid0000-0001-7084-6210cs
dc.identifier.orcid0000-0001-5286-9574cs
dc.identifier.other165021cs
dc.identifier.researcheridG-4209-2017cs
dc.identifier.researcheridE-3929-2018cs
dc.identifier.researcheridDZG-2188-2022cs
dc.identifier.scopus21834721500cs
dc.identifier.scopus23011945600cs
dc.identifier.scopus36167253100cs
dc.identifier.scopus9333762000cs
dc.identifier.urihttp://hdl.handle.net/11012/195248
dc.language.isoencs
dc.publisherIEEEcs
dc.relation.ispartofIEEE Accesscs
dc.relation.urihttps://ieeexplore.ieee.org/document/9159558cs
dc.rightsCreative Commons Attribution 4.0 Internationalcs
dc.rights.accessopenAccesscs
dc.rights.sherpahttp://www.sherpa.ac.uk/romeo/issn/2169-3536/cs
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/cs
dc.subjectCapacitanceen
dc.subjectResistanceen
dc.subjectCapacitorsen
dc.subjectTopologyen
dc.subjectTuningen
dc.subjectImpedanceen
dc.subjectAttenuationen
dc.subjectAdjustabilityen
dc.subjectcapacitance multiplicationen
dc.subjectcurrent conveyoren
dc.subjectcurrent gainen
dc.subjectdifferential voltage bufferen
dc.subjectelectronic tuningen
dc.subjectmultiplication factor adjustmenten
dc.subjectvoltage gainen
dc.titleCapacitance Multiplier Using Small Values of Multiplication Factors for Adjustability Extension and Parasitic Resistance Cancellation Techniqueen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
sync.item.dbidVAV-165021en
sync.item.dbtypeVAVen
sync.item.insts2025.02.03 15:41:34en
sync.item.modts2025.01.17 16:39:22en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav radioelektronikycs
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav telekomunikacícs
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