Reduced Check Node Storage for Hardware-Efficient LDPC Decoder

Abstract

This paper proposes a hardware- and memory-efficient architecture for Low-Density Parity-Check (LDPC) decoding, targeting enhanced-performance applications with constrained resources. The design integrates two novel techniques: (i) the Variable Single minimum Min-Sum (VSMS) algorithm, which reduces hardware complexity by identifying the first minimum value and its position during check node processing, while improving error correction through a correction factor applied in variable node updates; and (ii) a memory splitting strategy that exploits the structural properties of LDPC codes to optimize memory usage. Implementation on a Xilinx Kintex UltraScale+ (xcku5p) FPGA demonstrates a reduction in storage requirements by over 46.2% compared to conventional decoders. Furthermore, the proposed decoder achieves a performance gain of up to 0.38 dB at a Bit Error Rate (BER) of 10⁻⁸, outperforming traditional Min-Sum-based approaches.