Flood attacks generation

Simple item page
but.event.date28.04.2016cs
but.event.titleStudent EEICT 2016cs
dc.contributor.authorHudec, David
dc.date.accessioned2018-07-10T12:48:08Z
dc.date.available2018-07-10T12:48:08Z
dc.date.issued2016cs
dc.description.abstractProposal of a high speed packet flooding device is presented in this paper. The product is based on the FPGA (Field-programmable Gate Array) platform, developed in VHDL (Very high speed integrated circuit Hardware Description Language) and set into the NetCOPE environment. It uses an existing solution of packet generator. Once done, it should be implemented on a COMBO-80G board to serve as a network stressing tool.en
dc.formattextcs
dc.format.extent25-27cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationProceedings of the 22nd Conference STUDENT EEICT 2016. s. 25-27. ISBN 978-80-214-5350-0cs
dc.identifier.isbn978-80-214-5350-0
dc.identifier.urihttp://hdl.handle.net/11012/83862
dc.language.isoencs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings of the 22nd Conference STUDENT EEICT 2016en
dc.relation.urihttp://www.feec.vutbr.cz/EEICT/cs
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.rights.accessopenAccessen
dc.subjectFPGAen
dc.subjectVHDLen
dc.subjectNetCOPEen
dc.subjectDenial of Serviceen
dc.subjectDoSen
dc.subjectnetwork attacken
dc.subjectnetwork testeren
dc.subjectpacket generatoren
dc.titleFlood attacks generationen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
25-hudec.pdf
Size:
524.16 KB
Format:
Adobe Portable Document Format
Description:
Download
Collections
Student EEICT 2016