Flood attacks generation
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Date
Authors
Hudec, David
Advisor
Referee
Mark
Journal Title
Journal ISSN
Volume Title
Publisher
Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
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Abstract
Proposal of a high speed packet flooding device is presented in this paper. The product is based on the FPGA (Field-programmable Gate Array) platform, developed in VHDL (Very high speed integrated circuit Hardware Description Language) and set into the NetCOPE environment. It uses an existing solution of packet generator. Once done, it should be implemented on a COMBO-80G board to serve as a network stressing tool.
Description
Keywords
FPGA , VHDL , NetCOPE , Denial of Service , DoS , network attack , network tester , packet generator
Citation
Proceedings of the 22nd Conference STUDENT EEICT 2016. s. 25-27. ISBN 978-80-214-5350-0
http://www.feec.vutbr.cz/EEICT/
http://www.feec.vutbr.cz/EEICT/
Document type
Peer-reviewed
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Published version
Date of access to the full text
Language of document
en