Comparison of MOSFET Gate Waffle Patterns Based on Specific On-Resistance

This article describes waffle power MOSFET segmentation and defines its analytic models. Although waffle gate pattern is well-known architecture for effective channel scaling without requirements on process modification, no until today precise model considering segmentation of MOSFETs with waffle gate patterns, due to bulk connections, has been there proposed. Two different MOSFET topologies with gate waffle patterns have been investigated and compared with the same on-resistance of a standard MOSFET with finger gate pattern. The first one with diagonal metal interconnections allows reaching more than 40 % area reduction. The second MOSFET with the more simple orthogonal metal interconnections allows saving more than 20 % area. Moreover, new models defining conditions where segmented power MOSFETs with waffle gate patterns occupy less area than the standard MOSFET with finger gate pattern, have been introduced.

Keywords

Power MOSFET, waffle MOSFET, specific on-resistance, integrated circuits

Citation

Radioengineering. 2019 vol. 28, č. 3, s. 598-609. ISSN 1210-2512
https://www.radioeng.cz/fulltexts/2019/19_03_0598_0609.pdf

Document type

Peer-reviewed

Document version

Published version

Language of document

en

Document licence

Creative Commons Attribution 4.0 International license
http://creativecommons.org/licenses/by/4.0/