Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

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dc.contributor.authorKral, V.
dc.coverage.issue4cs
dc.coverage.volume32cs
dc.date.accessioned2024-01-09T14:20:54Z
dc.date.available2024-01-09T14:20:54Z
dc.date.issued2023-12cs
dc.description.abstractThis paper presents a new multi-bit pulse latch design that places innovative emphasis on the integration of scan input for automatic test pattern generation (ATPG). Two different designs have been developed in ONK65 technology (65 nm process): the first with standard threshold voltage (SVT) tailored for consumer products and the second with high threshold voltage (HVT) for automotive, each addressing specific aspects of process, voltage, and temperature (PVT). Multi-bit pulse latches offer a more efficient alternative to multi-bit flip-flop circuits and promise significant power and area savings. However, the efficiency of these latches depends on the technology, library type and customer requirements. A multi-bit pulse latch consists of a pulse generator and a pulsed latch. Each component is carefully designed for its specific purpose and the most appropriate topology is selected. Furthermore, the paper serves as a comprehensive guide to the design of low-power digital cells. It rethinks the topology design approach by emphasizing the scan input and presents simulation results for both components of the multi-bit pulse latch, highlighting their advantages. The results show that a less strict PVT offers greater benefits than a strict PVT.en
dc.formattextcs
dc.format.extent557-567cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2023 vol. 32, č. 4, s. 557-567. ISSN 1210-2512cs
dc.identifier.doi10.13164/re.2023.0557en
dc.identifier.issn1210-2512
dc.identifier.urihttps://hdl.handle.net/11012/244215
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttps://www.radioeng.cz/fulltexts/2023/23_04_0557_0567.pdfcs
dc.rightsCreative Commons Attribution 4.0 International licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subject5G chipsen
dc.subjectarea-friendly designen
dc.subjectautomotiveen
dc.subjectconsumer flip-flopsen
dc.subjectdigital standard cellen
dc.subjectdynamic poweren
dc.subjectleakageen
dc.subjectlow power chipsen
dc.subjectmulti-bit pulsed latchen
dc.subjectpulsed latchen
dc.subjectsaving areaen
dc.subjectscan modeen
dc.subjectserial shifteren
dc.subjectstatic poweren
dc.titleDesign of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technologyen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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