Design of Multi-bit Pulsed Latches with Scan Input in CMOS ONK65 Technology

Abstract

This paper presents a new multi-bit pulse latch design that places innovative emphasis on the integration of scan input for automatic test pattern generation (ATPG). Two different designs have been developed in ONK65 technology (65 nm process): the first with standard threshold voltage (SVT) tailored for consumer products and the second with high threshold voltage (HVT) for automotive, each addressing specific aspects of process, voltage, and temperature (PVT). Multi-bit pulse latches offer a more efficient alternative to multi-bit flip-flop circuits and promise significant power and area savings. However, the efficiency of these latches depends on the technology, library type and customer requirements. A multi-bit pulse latch consists of a pulse generator and a pulsed latch. Each component is carefully designed for its specific purpose and the most appropriate topology is selected. Furthermore, the paper serves as a comprehensive guide to the design of low-power digital cells. It rethinks the topology design approach by emphasizing the scan input and presents simulation results for both components of the multi-bit pulse latch, highlighting their advantages. The results show that a less strict PVT offers greater benefits than a strict PVT.