All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor
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Date
2018-08-05
Authors
Herencsár, Norbert
Kartci, Aslihan
Tlelo-Cuautle, Esteban
Metin, Bilgin
Cicekoglu, Oguzhan
0000-0002-9504-2275Advisor
Referee
Mark
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IEEE
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Abstract
Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.
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Citation
Proceedings of the 2018 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS). 2018, p. 129-132.
https://ieeexplore.ieee.org/document/8624059
https://ieeexplore.ieee.org/document/8624059
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Peer-reviewed
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Accepted version
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en
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(C) IEEE