All-Pass Time Delay Circuit Magnitude Response Optimization Using Fractional-Order Capacitor

Abstract

Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.Paper presents the integer- and fractional-order cases of a voltage-mode all-pass time delay circuit, or more frequently called as all-pass filter, employing a single negative-type current-controlled current inverting transconductance amplifier and a floating capacitor. Utilization of a fractional-order capacitor (FoC) C0,06 with 12 pF " sec.04 value for magnitude response optimization of the filter is investigated. FoC was emulated via 4th-order Valsa RC network and values optimized using modified least squares quadratic method. In frequency range MHz-I GlIz it shows only +0.5 degree phase angle deviation and the relative pseudo-capacitance error varies from-1.85% to +0.73%. SPICE simulations are given to prove the theory.