Instruction Mapping Process on the VLIW Architectures

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but.event.date28.04.2016cs
but.event.titleStudent EEICT 2016cs
dc.contributor.authorMego, Roman
dc.date.accessioned2018-07-10T12:48:17Z
dc.date.available2018-07-10T12:48:17Z
dc.date.issued2016cs
dc.description.abstractThis paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.en
dc.formattextcs
dc.format.extent385-389cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationProceedings of the 22nd Conference STUDENT EEICT 2016. s. 385-389. ISBN 978-80-214-5350-0cs
dc.identifier.isbn978-80-214-5350-0
dc.identifier.urihttp://hdl.handle.net/11012/83961
dc.language.isoencs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings of the 22nd Conference STUDENT EEICT 2016en
dc.relation.urihttp://www.feec.vutbr.cz/EEICT/cs
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.rights.accessopenAccessen
dc.subjectinstruction mappingen
dc.subjectlow-levelen
dc.subjectdigital signal processingen
dc.subjectvery long instruction worden
dc.titleInstruction Mapping Process on the VLIW Architecturesen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
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