Instruction Mapping Process on the VLIW Architectures
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Date
Authors
Mego, Roman
Advisor
Referee
Mark
Journal Title
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Volume Title
Publisher
Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
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Abstract
This paper deals with the process of instruction mapping on the digital signal processors. This process is used by the newly developed tool, which is designed for generating low-level assembly code for very long instruction word processors. The tool is suitable for creating cores of the signal processing algorithms.
Description
Citation
Proceedings of the 22nd Conference STUDENT EEICT 2016. s. 385-389. ISBN 978-80-214-5350-0
http://www.feec.vutbr.cz/EEICT/
http://www.feec.vutbr.cz/EEICT/
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Peer-reviewed
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en