The Tesseral Processor for Image Processing Based on Hierarchical Data Structures

dc.contributor.author	Harakal, M.
dc.contributor.author	Chmurny, J.
dc.coverage.issue	4	cs
dc.coverage.volume	6	cs
dc.date.accessioned	2016-05-05T12:02:11Z
dc.date.available	2016-05-05T12:02:11Z
dc.date.issued	1997-12	cs
dc.description.abstract	This paper describes the design and hardware implementation of the Tesseral Processor (TP) with Programmable Logic Devices (PLD). The TP can be used for image processing based on hierarchical data structures as Linear QuadTree (LQT).	en
dc.format	text	cs
dc.format.extent	1-5	cs
dc.format.mimetype	application/pdf	en
dc.identifier.citation	Radioengineering. 1997, vol. 6, č. 4, s. 1-5. ISSN 1210-2512	cs
dc.identifier.issn	1210-2512
dc.identifier.uri	http://hdl.handle.net/11012/58371
dc.language.iso	en	cs
dc.publisher	Radioengineering Society	cs
dc.relation.ispartof	Radioengineering	cs
dc.relation.uri	http://www.radioeng.cz/fulltexts/1997/97_04_01.pdf	cs
dc.rights	Creative Commons Attribution 3.0 Unported License	en
dc.rights.access	openAccess	en
dc.rights.uri	http://creativecommons.org/licenses/by/3.0/	en
dc.subject	quadtree representation	en
dc.subject	linear quadtree	en
dc.subject	tesseral addressing	en
dc.subject	tesseral arithmetic	en
dc.subject	tesseral arithmetic unit	en
dc.subject	tesseral control unit	en
dc.subject	tesseral processor	en
dc.title	The Tesseral Processor for Image Processing Based on Hierarchical Data Structures	en
dc.type.driver	article	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en
eprints.affiliatedInstitution.faculty	Fakulta elektrotechniky a komunikačních technologií	cs

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