The Tesseral Processor for Image Processing Based on Hierarchical Data Structures

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97_04_01.pdf (421.5 KB)

Date

1997-12

Authors

Harakal, M.
Chmurny, J.

Advisor

Referee

Mark

Journal Title

Journal ISSN

Volume Title

Publisher

Společnost pro radioelektronické inženýrství

ORCID

Abstract

This paper describes the design and hardware implementation of the Tesseral Processor (TP) with Programmable Logic Devices (PLD). The TP can be used for image processing based on hierarchical data structures as Linear QuadTree (LQT).

Description

Keywords

quadtree representation , linear quadtree , tesseral addressing , tesseral arithmetic , tesseral arithmetic unit , tesseral control unit , tesseral processor

Citation

Radioengineering. 1997, vol. 6, č. 4, s. 1-5. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/1997/97_04_01.pdf

Document type

Peer-reviewed

Document version

Published version

Date of access to the full text

Language of document

en

Study field

Comittee

Date of acceptance

Defence

Result of defence

DOI

URI

http://hdl.handle.net/11012/58371

Collections

1997/4

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Creative Commons license

Creative Commons Attribution 3.0 Unported License
Except where otherwised noted, this item's license is described as Creative Commons Attribution 3.0 Unported License
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