Analogue Implementation of a Fractional-Order PI^{\lambda} Controller for DC Motor Speed Control

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Herencsár, Norbert
Kartci, Aslihan
Koton, Jaroslav
Šotner, Roman
Alagoz, Baris Baykant
Yeroglu, Celaleddin

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Mark

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IEEE
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In this paper, an approach to design a fractional-order integral operator s(lambda) where -1 < lambda <0, using an analogue technique, is presented. The integrator with a constant phase angle -80.1 degree (i.e. order lambda = -0.89), bandwidth greater than 3 decades, and maximum relative phase error 1.38% is designed by cascade connection of first-order bilinear transfer segments and first-order low-pass filter. The performance of suggested realization is demonstrated in a fractional-order proportional-integral (FOPI lambda) controller described with proportional constant 1.37 and integration constant 2.28. The design specification corresponds to a speed control system of an armature controlled DC motor, which is often used in mechatronic and other fields of control theory. The behavior of both proposed analogue circuits employing two-stage Op-Amps is confirmed by SPICE simulations using TSMC 0.18 mu m level-7 LA) EN SCN018 CMOS process parameters with +/- 0.9 V supply voltages.
In this paper, an approach to design a fractional-order integral operator s(lambda) where -1 < lambda <0, using an analogue technique, is presented. The integrator with a constant phase angle -80.1 degree (i.e. order lambda = -0.89), bandwidth greater than 3 decades, and maximum relative phase error 1.38% is designed by cascade connection of first-order bilinear transfer segments and first-order low-pass filter. The performance of suggested realization is demonstrated in a fractional-order proportional-integral (FOPI lambda) controller described with proportional constant 1.37 and integration constant 2.28. The design specification corresponds to a speed control system of an armature controlled DC motor, which is often used in mechatronic and other fields of control theory. The behavior of both proposed analogue circuits employing two-stage Op-Amps is confirmed by SPICE simulations using TSMC 0.18 mu m level-7 LA) EN SCN018 CMOS process parameters with +/- 0.9 V supply voltages.

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Proceedings of the 2019 IEEE 28th International Symposium on Industrial Electronics (ISIE), Vancouver, Canada. 2019, p. 467-472.
https://doi.org/10.1109/ISIE.2019.8781237

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en

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