0.3-V, 357.4-nW Voltage-Mode First-Order Analog Filter Using a Multiple-Input VDDDA

Abstract

In this paper, a new versatile first-order voltage-mode analog filter using a single multiple-input voltage differencing differential difference amplifier for extremely low-voltage supply and low-frequency applications is presented. Using multiple-input MOS transistor technique, the filter can realize the first-order transfer functions of non-inverting and inverting low-pass, high-pass, and all-pass filters in a single topology with high input and low output impedance. This is particularly useful for voltage-mode circuits. The filter's pole frequency can be controlled electronically. The filter was used to implement a new quadrature oscillator to confirm its advantages. The multiple-input was applied to bulk-driven differential pairs operating in weak inversion; therefore, the proposed circuit operated from a supply voltage of 0.3 V and consumed 357.4 nW. The circuit was designed in the Cadence program using 0.13 mu m UMC CMOS technology. The performance and robustness of the design was validated by intensive simulations, including Monte Carlo and Process, Voltage and Temperature corner analyses.In this paper, a new versatile first-order voltage-mode analog filter using a single multiple-input voltage differencing differential difference amplifier for extremely low-voltage supply and low-frequency applications is presented. Using multiple-input MOS transistor technique, the filter can realize the first-order transfer functions of non-inverting and inverting low-pass, high-pass, and all-pass filters in a single topology with high input and low output impedance. This is particularly useful for voltage-mode circuits. The filter's pole frequency can be controlled electronically. The filter was used to implement a new quadrature oscillator to confirm its advantages. The multiple-input was applied to bulk-driven differential pairs operating in weak inversion; therefore, the proposed circuit operated from a supply voltage of 0.3 V and consumed 357.4 nW. The circuit was designed in the Cadence program using 0.13 mu m UMC CMOS technology. The performance and robustness of the design was validated by intensive simulations, including Monte Carlo and Process, Voltage and Temperature corner analyses.