VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Simple item page
but.event.date26.04.2022cs
but.event.titleSTUDENT EEICT 2022cs
dc.contributor.authorJedlicka, Petr
dc.contributor.authorHajny, Jan
dc.date.accessioned2022-12-06T13:22:00Z
dc.date.available2022-12-06T13:22:00Z
dc.date.issued2022cs
dc.description.abstractCRYSTALS-Kyber is one of the finalists of the National Institute of Standards and Technology (NIST) post-quantum cryptography competition. In this paper, we deal with effective hardware-accelerated implementations of components intended for the use in the FPGA (Field Programmable Gate Array) implementation of the above-mentioned lattice-based cryptography scheme. The discussed components are NTT (Number Theoretic Transform), inverse NTT (NTT−1), CBD (Centered Binomial Distribution) and the Parse Algorithm (shortly Parse). The improved implementation of NTT (NTT−1) requires 1189 (1568) Look-Up Tables (LUTs), 1469 (2161) Flip-Flops (FFs), 28 (50) Digital Signal Processing blocks (DSPs) and 1.5 (1.5) Block Memories (BRAMs). The latency of the design is 322 (334) clock cycles at the frequency 637 MHz which makes the presented NTT (NTT−1) implementations to be currently the fastest ones. The implementations of the sampling functions (CBD and Parse) requires less than 100 LUTs and FFs with maximum latency 5 clock cycles at the frequencies over 700 Mhz. All implementations has been synthesized for the Xilinx Virtex UltraScale+ architecture.en
dc.formattextcs
dc.format.extent297-301cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationProceedings II of the 28st Conference STUDENT EEICT 2022: Selected papers. s. 297-301. ISBN 978-80-214-6030-0cs
dc.identifier.doi10.13164/eeict.2022.297
dc.identifier.isbn978-80-214-6030-0
dc.identifier.urihttp://hdl.handle.net/11012/208656
dc.language.isoencs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings II of the 28st Conference STUDENT EEICT 2022: Selected papersen
dc.relation.urihttps://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazenics
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.rights.accessopenAccessen
dc.subjectNTT, CBD, Parse, VHDL, FPGA, Kyberen
dc.titleVHDL-based implementation of CRYSTALS-Kyber components on FPGAen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
Files
Original bundle
Now showing 1 - 1 of 1
Thumbnail Image
Name:
297_eeict_2022.pdf
Size:
1.05 MB
Format:
Adobe Portable Document Format
Description:
Download
Collections
Student EEICT 2022: Selected Papers