VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Jedlicka, Petr; Hajny, Jan

VHDL-based implementation of CRYSTALS-Kyber components on FPGA

Files

297_eeict_2022.pdf(1.05 MB)

Date

2022

Authors

Jedlicka, Petr

Hajny, Jan

Publisher

Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií

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Abstract

CRYSTALS-Kyber is one of the finalists of the National Institute of Standards and Technology (NIST) post-quantum cryptography competition. In this paper, we deal with effective hardware-accelerated implementations of components intended for the use in the FPGA (Field Programmable Gate Array) implementation of the above-mentioned lattice-based cryptography scheme. The discussed components are NTT (Number Theoretic Transform), inverse NTT (NTT−1), CBD (Centered Binomial Distribution) and the Parse Algorithm (shortly Parse). The improved implementation of NTT (NTT−1) requires 1189 (1568) Look-Up Tables (LUTs), 1469 (2161) Flip-Flops (FFs), 28 (50) Digital Signal Processing blocks (DSPs) and 1.5 (1.5) Block Memories (BRAMs). The latency of the design is 322 (334) clock cycles at the frequency 637 MHz which makes the presented NTT (NTT−1) implementations to be currently the fastest ones. The implementations of the sampling functions (CBD and Parse) requires less than 100 LUTs and FFs with maximum latency 5 clock cycles at the frequencies over 700 Mhz. All implementations has been synthesized for the Xilinx Virtex UltraScale+ architecture.

Keywords

NTT, CBD, Parse, VHDL, FPGA, Kyber

Citation

Proceedings II of the 28st Conference STUDENT EEICT 2022: Selected papers. s. 297-301. ISBN 978-80-214-6030-0
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni

Document type

Peer-reviewed

Document version

Published version

Language of document

en

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