Acceleration Unit for HTTP Headers Identification in FPGA
| but.event.date | 23.04.2015 | cs |
| but.event.title | Student EEICT 2015 | cs |
| dc.contributor.author | Bryndza, Ivan | |
| dc.date.accessioned | 2015-08-25T08:42:46Z | |
| dc.date.available | 2015-08-25T08:42:46Z | |
| dc.date.issued | 2015 | cs |
| dc.description.abstract | This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match. | en |
| dc.format | text | cs |
| dc.format.extent | 34-36 | cs |
| dc.format.mimetype | application/pdf | en |
| dc.identifier.citation | Proceedings of the 21st Conference STUDENT EEICT 2015. s. 34-36. ISBN 978-80-214-5148-3 | cs |
| dc.identifier.isbn | 978-80-214-5148-3 | |
| dc.identifier.uri | http://hdl.handle.net/11012/42922 | |
| dc.language.iso | cs | cs |
| dc.publisher | Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
| dc.relation.ispartof | Proceedings of the 21st Conference STUDENT EEICT 2015 | en |
| dc.relation.uri | http://www.feec.vutbr.cz/EEICT/ | cs |
| dc.rights | © Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
| dc.rights.access | openAccess | en |
| dc.subject | HTTP | en |
| dc.subject | Nondeterministic Finite Automata (NFA) | en |
| dc.subject | BRAM | en |
| dc.subject | Field Programmable Gate Array (FPGA) | en |
| dc.title | Acceleration Unit for HTTP Headers Identification in FPGA | en |
| dc.type.driver | conferenceObject | en |
| dc.type.status | Peer-reviewed | en |
| dc.type.version | publishedVersion | en |
| eprints.affiliatedInstitution.department | Fakulta elektrotechniky a komunikačních technologií | cs |