Acceleration Unit for HTTP Headers Identification in FPGA

Abstract

This paper presents a hardware accelerated identification of HTTP protocol headers, since HTTP is the most used protocol on the Internet. We have designed a hardware architecture, which will be used for detection of HTTP header in each packet. Architecture will be able to achieve the throughput needed for monitoring of 100 Gb/s networks. Nondeterministic finite automata and massive parallelism is used for pattern match.