Lattice-based Threshold Signature Optimization for RAM Constrained Devices

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but.event.date23.04.2024cs
but.event.titleSTUDENT EEICT 2024cs
dc.contributor.authorShapoval, Vladyslav
dc.contributor.authorRicci, Sara
dc.date.accessioned2024-07-09T07:38:37Z
dc.date.available2024-07-09T07:38:37Z
dc.date.issued2024cs
dc.description.abstractThe DS2 scheme is a lattice-based (n, n)-threshold signature based on the standardized Dilithium signature. However, deploying DS2, as well as Dilithium, on microcontrollers is a challenge due to the memory limitations of these devices. While the decryption phase can be implemented relatively straightforwardly, the key generation and signing phases require the generation and manipulation of large matrices and vectors, which can quickly exhaust the available memory on the microcontroller. In this paper, we propose an optimization of the DS2 key generation and signing algorithms tailored for microcontrollers. Our approach focuses on minimizing memory consumption by generating large elements, such as the commitment key ck and the random commitment parameter r, on the fly from random and non-random seeds. This approach significantly reduces the overall size of the signature from 143 KB to less than 5 KB, depending on the number of signers involved. We also split the algorithms into two distinct components: a security-critical part and a non-security-critical part. The security-critical part contains operations that require secret knowledge and must be run on the microcontroller itself. Conversely, the non-critical part contains operations that do not require secret knowledge and can be performed on a connected, more powerful central host.en
dc.formattextcs
dc.format.extent147-150cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationProceedings I of the 30st Conference STUDENT EEICT 2024: General papers. s. 147-150. ISBN 978-80-214-6231-1cs
dc.identifier.isbn978-80-214-6231-1
dc.identifier.issn2788-1334
dc.identifier.urihttps://hdl.handle.net/11012/249219
dc.language.isoencs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings I of the 30st Conference STUDENT EEICT 2024: General papersen
dc.relation.urihttps://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdfcs
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.rights.accessopenAccessen
dc.subjectLattice-based cryptographyen
dc.subjectthreshold signatureen
dc.subjectmicro-controllersen
dc.subjectoptimizationen
dc.titleLattice-based Threshold Signature Optimization for RAM Constrained Devicesen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
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