An Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noise

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dc.contributor.authorKumar, M.
dc.contributor.authorMondal, A. J.
dc.coverage.issue2cs
dc.coverage.volume32cs
dc.date.accessioned2023-10-11T07:43:38Z
dc.date.available2023-10-11T07:43:38Z
dc.date.issued2023-06cs
dc.description.abstractDigital subsystem prefers CMOS process, but it is difficult to manage speed and average power (Pavg) trade-off in each era with power supply voltage (Vdd) scaling. Current mode logic (CML) has emerged as an alternative to design the fundamental block of a SerDes, namely, the latch. However, available CML circuits consume significant Pavg and suffer from rapid input slewing. Typically, fast switching inputs enable current flow to effective supply voltage VP and overcharges output. In fact, VP is different than externally applied Vdd and oscillates with time as and when an abrupt current is drawn. This affects delay td and introduces jitter. The topic presents a new latch for SerDes interface using a new current steering circuit and coupled to a power delivery network (PDN). The significant point is to attain an almost constant td in comparison to conventional designs while the Vdd changes. The post-layout results at 0.09-μm CMOS and 1.1 V Vdd indicate that the Pavg and td are 339.5 µW and 61.9 ps, respectively, at 27OC. Surprisingly, the td variation is noted to be minimum and the power supply noise induced jitter is around 1.5 ns when VP close to the circuit varies due to sudden current.en
dc.formattextcs
dc.format.extent207-220cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2023 vol. 32, č. 2, s. 207-220. ISSN 1210-2512cs
dc.identifier.doi10.13164/re.2023.0207en
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/214323
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttps://www.radioeng.cz/fulltexts/2023/23_02_0207_0220.pdfcs
dc.rightsCreative Commons Attribution 4.0 International licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/en
dc.subjectPDNen
dc.subjectlatchen
dc.subjectfigure of meriten
dc.subjectMonte Carloen
dc.subjectoutput noiseen
dc.subjectjitteren
dc.titleAn Improved Latch for SerDes Interface: Design and Analysis under PVT and AC Noiseen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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