An Area-Efficient and Low-Latency Analog Content-Addressable Memory Design Using gm/ID Methodology with Memristors

Abstract

In-memory computing (IMC) is an emerging approach to mitigating the memory bottleneck, a critical issue affecting energy efficiency and latency in modern digital computing. IMC operating in the analog domain can achieve high data density and accelerate signal processing tasks such as neural network training by leveraging nonvolatile memory technologies, specifically resistive switching devices. Conversely, content-addressable memories (CAMs), known for their inherent parallelism and fast digital lookup capabilities, are constrained by their large area and high energy consumption. To address these limitations, analog CAMs, which combine the analog domain with the tunability of memristors, have been proposed to enhance storage density and energy efficiency. In this work, we introduce a novel topology that reduces latency and area by employing the gm/ID design methodology to optimize the sizing of MOS devices. Utilizing the VTEAM model for simulations, our circuit achieves approximately twice the latency reduction compared to the 10T2M design, while occupying up to 66% less area. Additionally, our design exhibits the lowest latency among existing multi-bit and analog CAM approaches, reducing latency by 96%.