Improvement of Bit Error Rate in Free Space Optical Link
but.event.date | 28.04.2016 | cs |
but.event.title | Student EEICT 2016 | cs |
dc.contributor.author | Novák, Marek | |
dc.date.accessioned | 2018-07-10T12:48:12Z | |
dc.date.available | 2018-07-10T12:48:12Z | |
dc.date.issued | 2016 | cs |
dc.description.abstract | The article describes an inovative bit error rate reduction technique principle and its practical implementation. The design is implemented in an FPGA and can be combined with other more conventional BER reduction techniques. The presented approach benefits from properties of an optical channel which a general RF channel does not have. | en |
dc.format | text | cs |
dc.format.extent | 135-137 | cs |
dc.format.mimetype | application/pdf | en |
dc.identifier.citation | Proceedings of the 22nd Conference STUDENT EEICT 2016. s. 135-137. ISBN 978-80-214-5350-0 | cs |
dc.identifier.isbn | 978-80-214-5350-0 | |
dc.identifier.uri | http://hdl.handle.net/11012/83896 | |
dc.language.iso | en | cs |
dc.publisher | Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
dc.relation.ispartof | Proceedings of the 22nd Conference STUDENT EEICT 2016 | en |
dc.relation.uri | http://www.feec.vutbr.cz/EEICT/ | cs |
dc.rights | © Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií | cs |
dc.rights.access | openAccess | en |
dc.subject | BER | en |
dc.subject | FSO | en |
dc.subject | FIFO | en |
dc.subject | FPGA | en |
dc.subject | Xilinx MIG | en |
dc.title | Improvement of Bit Error Rate in Free Space Optical Link | en |
dc.type.driver | conferenceObject | en |
dc.type.status | Peer-reviewed | en |
dc.type.version | publishedVersion | en |
eprints.affiliatedInstitution.department | Fakulta elektrotechniky a komunikačních technologií | cs |
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