Universal asynchronous receiver/transmitter implementation in VHDL

but.event.date26.04.2022cs
but.event.titleSTUDENT EEICT 2022cs
dc.contributor.authorPrášil, Pavel
dc.contributor.authorPetyovský, Petr
dc.date.accessioned2023-04-25T10:17:06Z
dc.date.available2023-04-25T10:17:06Z
dc.date.issued2022cs
dc.description.abstractThe article deals with the design of an asynchronous serial receiver/transmitter and its implementation into the FPGA. The design will be used as a laboratory exercise in the course ”Logical circuits and systems”. This paper contains the basic design of UART and the following features which will be added. UART design will be used as a communication interface between PC and an existing programmable multichannel sound generator (PSG) design, which is already implemented in FPGA.en
dc.formattextcs
dc.format.extent68-71cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationProceedings I of the 28st Conference STUDENT EEICT 2022: General papers. s. 68-71. ISBN 978-80-214-6029-4cs
dc.identifier.isbn978-80-214-6029-4
dc.identifier.urihttp://hdl.handle.net/11012/209293
dc.language.isoencs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings I of the 28st Conference STUDENT EEICT 2022: General papersen
dc.relation.urihttps://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazenics
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.rights.accessopenAccessen
dc.subjectUARTen
dc.subjectFPGAen
dc.subjectVHDLen
dc.subjectprogrammable multichannel sound generatoren
dc.titleUniversal asynchronous receiver/transmitter implementation in VHDLen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
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