Universal asynchronous receiver/transmitter implementation in VHDL
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Date
2022
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Mark
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Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract
The article deals with the design of an asynchronous serial receiver/transmitter and its implementation into the FPGA. The design will be used as a laboratory exercise in the course ”Logical circuits and systems”. This paper contains the basic design of UART and the following features which will be added. UART design will be used as a communication interface between PC and an existing programmable multichannel sound generator (PSG) design, which is already implemented in FPGA.
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Proceedings I of the 28st Conference STUDENT EEICT 2022: General papers. s. 68-71. ISBN 978-80-214-6029-4
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
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Peer-reviewed
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en
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© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií