Analysis of Minimal LDPC Decoder System on a Chip Implementation

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dc.contributor.authorPalenik, Tomas
dc.contributor.authorFarkas, Peter
dc.contributor.authorRakus, Martin
dc.contributor.authorDobos, Jan
dc.coverage.issue3cs
dc.coverage.volume24cs
dc.date.accessioned2015-10-26T08:05:45Z
dc.date.available2015-10-26T08:05:45Z
dc.date.issued2015-09cs
dc.description.abstractThis paper presents a practical method of potential replacement of several different Quasi-Cyclic Low-Density Parity-Check (QC-LDPC) codes with one, with the intention of saving as much memory as required to implement the LDPC encoder and decoder in a memory-constrained System on a Chip (SoC). The presented method requires only a very small modification of the existing encoder and decoder, making it suitable for utilization in a Software Defined Radio (SDR) platform. Besides the analysis of the effects of necessary variable-node value fixation during the Belief Propagation (BP) decoding algorithm, practical standard-defined code parameters are scrutinized in order to evaluate the feasibility of the proposed LDPC setup simplification. Finally, the error performance of the modified system structure is evaluated and compared with the original system structure by means of simulation.en
dc.formattextcs
dc.format.extent783-790cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2015 vol. 24, č. 3, s. 783-790. ISSN 1210-2512cs
dc.identifier.doi10.13164/re.2015.0783en
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/51745
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2015/15_03_0783_0790.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectLDPC code shorteningen
dc.subjectSystem on a Chipen
dc.subjectfixed nodes decoderen
dc.subjectAdaptive Coding and Modulationen
dc.titleAnalysis of Minimal LDPC Decoder System on a Chip Implementationen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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