Versatile Chirp Sine Generator on Fix-point FPGA

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dc.contributor.authorKunz, Jancs
dc.contributor.authorBeneš, Petrcs
dc.coverage.issue6cs
dc.coverage.volume60cs
dc.date.issued2020-12-31cs
dc.description.abstractThis paper deals with a logarithmic and a linear chirp sine generation on a fixed-point FPGA mainly for vibration testing, nevertheless, the generator can also be used in other areas. A basic overview of the logarithmic chirp sine signal is provided. Then, methods of software signal generation as well as different hardware platforms are briefly described and their pros and cons are mentioned. A DDS generator on FPGA needs the phase difference between samples as an input. This generation for the logarithm chirp sine signal is presented, and its resolution, errors and limitations on fixed-point arithmetic are revealed. Our implementation runs on Compact RIO 9067, uses 32-bit fixed-point and is able to generate linear and logarithm chirp signals from 10 Hz to 7 kHz with a minimum chirp speed of 1 oct/min.en
dc.formattextcs
dc.format.extent462-468cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationActa Polytechnica (on-line). 2020, vol. 60, issue 6, p. 462-468.en
dc.identifier.doi10.14311/AP.2020.60.0462cs
dc.identifier.issn1805-2363cs
dc.identifier.orcid0000-0002-6917-7950cs
dc.identifier.orcid0000-0002-3712-7107cs
dc.identifier.other160854cs
dc.identifier.researcheridE-1200-2017cs
dc.identifier.researcheridB-1805-2008cs
dc.identifier.scopus7006828688cs
dc.identifier.urihttp://hdl.handle.net/11012/196548
dc.language.isoencs
dc.publisherCzech Technical University in Praguecs
dc.relation.ispartofActa Polytechnica (on-line)cs
dc.relation.urihttps://ojs.cvut.cz/ojs/index.php/ap/article/view/6049cs
dc.rightsCreative Commons Attribution 4.0 Internationalcs
dc.rights.accessopenAccesscs
dc.rights.sherpahttp://www.sherpa.ac.uk/romeo/issn/1805-2363/cs
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/cs
dc.subjectLinear Chirp Sineen
dc.subjectLogarithm Chirp Sineen
dc.subjectFPGAen
dc.subjectFix-pointen
dc.subjectGenerationen
dc.titleVersatile Chirp Sine Generator on Fix-point FPGAen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
sync.item.dbidVAV-160854en
sync.item.dbtypeVAVen
sync.item.insts2025.02.03 15:39:28en
sync.item.modts2025.01.17 16:35:45en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav automatizace a měřicí technikycs
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