Performance Analysis of Oustaloup Approximation for the Design of Fractional-Order Analogue Circuits

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dc.contributor.authorKoton, Jaroslavcs
dc.contributor.authorStavnesli, Jorgen Hagsetcs
dc.contributor.authorFreeborn, Toddcs
dc.date.accessioned2024-03-08T15:45:52Z
dc.date.available2024-03-08T15:45:52Z
dc.date.issued2018-11-05cs
dc.description.abstractThe description and definition of various systems using fractional-order calculus continues to gain attention in a variety of field of engineering. This is especially true for the design of analogue function blocks, where the factional-order Laplace operator s , whereas 0 < < 1, is frequently used to design the fractional to design the transfer functions of these blocks. In this paper we focus on analysing the Oustaloup approximation of s to provide a tool that can support selecting the appropriate approximation to obtain a response that satisfies the designers’ requirements of approximation error in magnitude and/or phase in a specific frequency range for the minimal possible order N of the approximationen
dc.formattextcs
dc.format.extent1-4cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationProceedings 10th International Congress on Ultra Modern Telecommunications and Control Systems - ICUMT 2018. 2018, p. 1-4.en
dc.identifier.doi10.1109/ICUMT.2018.8631227cs
dc.identifier.isbn978-1-5386-9361-2cs
dc.identifier.orcid0000-0003-4263-5875cs
dc.identifier.other151272cs
dc.identifier.researcheridE-1241-2018cs
dc.identifier.scopus15061338400cs
dc.identifier.urihttps://hdl.handle.net/11012/245261
dc.language.isoencs
dc.publisherIEEEcs
dc.relation.ispartofProceedings 10th International Congress on Ultra Modern Telecommunications and Control Systems - ICUMT 2018cs
dc.relation.urihttps://ieeexplore.ieee.org/document/8631227cs
dc.rights(C) IEEEcs
dc.rights.accessopenAccesscs
dc.subjectfractional-order calculusen
dc.subjectOustaloup approximationen
dc.subjectanalogue circuit designen
dc.titlePerformance Analysis of Oustaloup Approximation for the Design of Fractional-Order Analogue Circuitsen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionacceptedVersionen
sync.item.dbidVAV-151272en
sync.item.dbtypeVAVen
sync.item.insts2024.03.08 16:45:52en
sync.item.modts2024.03.08 16:13:05en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav telekomunikacícs
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. oddělení-TKO-SIXcs
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