A 28-nm 32Kb SRAM For Low-VMIN Applications Using Write and Read Assist Techniques

Abstract

In this paper new write and read assist techniques, reduced coupling signal negative bitline (RCS-NBL) and low power disturbance noise reduction (LP-DNR) of 6T static random-access memory (SRAM) to improve its minimal supply voltage (VMIN), have been presented. To observe the improvements in VMIN and power consumption of SRAM with the help of proposed assist techniques, a 32 Kb capacity SRAM, with 128 words of 256 bits width, is designed and simulated in 28-nm bulk CMOS technology. New RCS-NBL scheme, shows an improvement in SRAM write VMIN by 295 mV and also reduces overstress on pass transistor (PG) of the selected bitcell by 40 mV. Proposed LP-DNR scheme demonstrates an improvement in SRAM read VMIN by 35 mV and also shows a saving of the power loss in the existing DNR scheme during the read access which occurs due to continuous flow of current from the cross coupled latch to the discharge block path after the bitlines have settled. The static power consumption of this SRAM macro is improved by 48.9 % and 11.7 % while dynamic power by 91.7 % and 8.1 % with the help of proposed write and read assist techniques respectively. Area overheads of these proposed RCS-NBL and LP-DNR assist techniques for this macro are less than 0.79 % and 3.70 % respectively.