Novel FDNR, FDNC and lossy inductor simulators employing second generation voltage conveyor (VCII)

Abstract

In this research the second-generation voltage conveyor (VCII) is employed in the design of grounded frequency dependent negative resistor (FDNR) and Frequency dependent negative conductance (FDNC). Additionally, two lossy parallel and series R-L inductor simulators are also designed. To the best knowledge of the authors above mentioned immittance simulators are first time implemented using VCII. The FDNR requires two VCII, two capacitors and one grounded resistor. FDNC is implemented using three VCII, three resistors and two grounded capacitors. The R-L inductor emulators requires two VCII, two resistors and one grounded capacitor. All the presented immittance simulators do not require any kind of passive component matching. The non-ideal gain and sensitivity analysis is conducted to study their performance under circuit parameter variations. Parasitic analysis is also done for the FDNR, FDNC and R-L inductance simulators to study the effect of parasitic impedance on the circuit operation. To validate the designs, they are simulated in Cadence design environment using 0.18 mu m process design kit (PDK) at +/- 0.9 V supply. Additionally, the circuits are also validated using the macro model of commercially available integrated circuit (IC) AD844. The theoretical and simulation results are found to be in close agreement.In this research the second-generation voltage conveyor (VCII) is employed in the design of grounded frequency dependent negative resistor (FDNR) and Frequency dependent negative conductance (FDNC). Additionally, two lossy parallel and series R-L inductor simulators are also designed. To the best knowledge of the authors above mentioned immittance simulators are first time implemented using VCII. The FDNR requires two VCII, two capacitors and one grounded resistor. FDNC is implemented using three VCII, three resistors and two grounded capacitors. The R-L inductor emulators requires two VCII, two resistors and one grounded capacitor. All the presented immittance simulators do not require any kind of passive component matching. The non-ideal gain and sensitivity analysis is conducted to study their performance under circuit parameter variations. Parasitic analysis is also done for the FDNR, FDNC and R-L inductance simulators to study the effect of parasitic impedance on the circuit operation. To validate the designs, they are simulated in Cadence design environment using 0.18 mu m process design kit (PDK) at +/- 0.9 V supply. Additionally, the circuits are also validated using the macro model of commercially available integrated circuit (IC) AD844. The theoretical and simulation results are found to be in close agreement.