FPGA Based Test Module for Error Bit Evaluation in Serial Links

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dc.contributor.authorKolouch, Jaromir
dc.coverage.issue1cs
dc.coverage.volume15cs
dc.date.accessioned2016-04-22T06:14:26Z
dc.date.available2016-04-22T06:14:26Z
dc.date.issued2006-04cs
dc.description.abstractA test module for serial links is described. In the link transmitter, one module generates pseudorandom pulse signal that is transmitted by the link. Second module located in the link receiver generates the same signal and compares it to the received signal. Errors caused by the signal transmission can be then detected and results sent to a master computer for further processing like statistical evaluation. The module can be used for long-term error monitoring without need for human operator presence.en
dc.formattextcs
dc.format.extent38-41cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationRadioengineering. 2006, vol. 15, č. 1, s. 38-41. ISSN 1210-2512cs
dc.identifier.issn1210-2512
dc.identifier.urihttp://hdl.handle.net/11012/57944
dc.language.isoencs
dc.publisherSpolečnost pro radioelektronické inženýrstvícs
dc.relation.ispartofRadioengineeringcs
dc.relation.urihttp://www.radioeng.cz/fulltexts/2006/06_01_38_41.pdfcs
dc.rightsCreative Commons Attribution 3.0 Unported Licenseen
dc.rights.accessopenAccessen
dc.rights.urihttp://creativecommons.org/licenses/by/3.0/en
dc.subjectSerial linken
dc.subjectbit error rateen
dc.subjectLFSR counteren
dc.subjectfree-space optical linken
dc.subjectFPGAen
dc.titleFPGA Based Test Module for Error Bit Evaluation in Serial Linksen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.facultyFakulta eletrotechniky a komunikačních technologiícs
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