Low-latency AES encryption for High-Frequency Trading on FPGA

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but.event.date23.04.2024cs
but.event.titleSTUDENT EEICT 2024cs
dc.contributor.authorCíbik, Peter
dc.contributor.authorRůžek, Michal
dc.contributor.authorDvořák, Milan
dc.date.accessioned2024-07-09T07:38:39Z
dc.date.available2024-07-09T07:38:39Z
dc.date.issued2024cs
dc.description.abstractThis paper presents a Field Programmable Gate Array (FPGA) powered low–latency solution for secure communication with the stock exchange. It presents architecture design and optimization techniques used to ensure the required security level without impacting the latency, which is the most critical domain in High-Frequency Trading (HFT). The National Stock Exchange of India (NSE) chose Advanced Encryption Standard (AES) with 256 bit key length in Galoise-Counter Mode (GCM) as the encryption algorithm for Non-NEAT Front End (NNF) connections.en
dc.formattextcs
dc.format.extent236-240cs
dc.format.mimetypeapplication/pdfen
dc.identifier.citationProceedings I of the 30st Conference STUDENT EEICT 2024: General papers. s. 236-240. ISBN 978-80-214-6231-1cs
dc.identifier.isbn978-80-214-6231-1
dc.identifier.issn2788-1334
dc.identifier.urihttps://hdl.handle.net/11012/249242
dc.language.isoencs
dc.publisherVysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.relation.ispartofProceedings I of the 30st Conference STUDENT EEICT 2024: General papersen
dc.relation.urihttps://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdfcs
dc.rights© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologiícs
dc.rights.accessopenAccessen
dc.subjectField–Programmable Gate Arrayen
dc.subjectFPGAen
dc.subjectHigh- Frequency Tradingen
dc.subjectHFTen
dc.subjectNational Stock Exchange of Indiaen
dc.subjectNSEen
dc.subjectCryptographyen
dc.subjectHardware accelerationen
dc.subjectVHDLen
dc.subjectEncryptionen
dc.subjectDecryptionen
dc.subjectAESen
dc.subjectGCMen
dc.titleLow-latency AES encryption for High-Frequency Trading on FPGAen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.affiliatedInstitution.departmentFakulta elektrotechniky a komunikačních technologiícs
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