Low-latency AES encryption for High-Frequency Trading on FPGA

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236-eeict-2024.pdf(862.42 KB)
Date
2024
Authors
Cíbik, Peter
Růžek, Michal
Dvořák, Milan
ORCID
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Referee
Mark
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Volume Title
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Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract
This paper presents a Field Programmable Gate Array (FPGA) powered low–latency solution for secure communication with the stock exchange. It presents architecture design and optimization techniques used to ensure the required security level without impacting the latency, which is the most critical domain in High-Frequency Trading (HFT). The National Stock Exchange of India (NSE) chose Advanced Encryption Standard (AES) with 256 bit key length in Galoise-Counter Mode (GCM) as the encryption algorithm for Non-NEAT Front End (NNF) connections.
Description
Keywords
Field–Programmable Gate Array, FPGA, High- Frequency Trading, HFT, National Stock Exchange of India, NSE, Cryptography, Hardware acceleration, VHDL, Encryption, Decryption, AES, GCM
Citation
Proceedings I of the 30st Conference STUDENT EEICT 2024: General papers. s. 236-240. ISBN 978-80-214-6231-1
https://www.eeict.cz/eeict_download/archiv/sborniky/EEICT_2024_sbornik_1.pdf
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Peer-reviewed
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Published version
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en
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© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
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https://hdl.handle.net/11012/249242
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Student EEICT 2024: General Papers
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