On reversibility of synchronous counters

Abstract

This paper gathers information about different types of counters, mainly linear feedbackshift registers, linear hybrid cellular automaton and binary counters. We explore their capability ofbeing reversed (counting in reverse order) and implementation of counters capable of counting inboth directions. In second part different types of counters are compared in required implementationresources when synthetizing for FPGA and also for standard cell library with word width rangingfrom 3 to 16bits. Selection of more resource optimal counter could leads to ASIC area saving around20–32 %.This paper gathers information about different types of counters, mainly linear feedbackshift registers, linear hybrid cellular automaton and binary counters. We explore their capability ofbeing reversed (counting in reverse order) and implementation of counters capable of counting inboth directions. In second part different types of counters are compared in required implementationresources when synthetizing for FPGA and also for standard cell library with word width rangingfrom 3 to 16bits. Selection of more resource optimal counter could leads to ASIC area saving around20–32 %.