Test Methods of PAL-, PLA-, and MAPL- Structures

Abstract

The architecture of various programmable logic arrays such as PAL (Programmable Array Logic), PLA (Programmable Logic Array) and MAPL (Multiple Array Programmable Logic) differ slightly in interconnection. The introduced types of devices are called PLD (Programmable Logic Devices). It is a bulk of programmable AND functions (product terms), and OR functions. The whole circuit structure is completed by input/output or dedicated output macrocells allowing to do the minimization of product term number. PLD's internal AND-array, and OR-array differs from the discrete logic AND, and OR devices whereas the functions are similar. The troubleshooting of these devices differs too.