Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

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dc.contributor.authorPetržela, Jiřícs
dc.contributor.authorŠotner, Romancs
dc.coverage.issue1cs
dc.coverage.volume8cs
dc.date.issued2020-11-01cs
dc.description.abstractThis work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) characteristics associated with PWL two-terminals to be electronically adjustable via external DC voltage. Numerical analysis of designed memory cell covers all mandatory parts: phase portraits, calculation of the largest Lyapunov exponent (LLE), basins of attraction for the typical strange attractors, and high resolution circuit-oriented bifurcation sequences. A transition from the stable states toward chaotic regime through metastability is proved via real measurement. The robustness of the generated chaotic attractors is verified by captured oscilloscope screenshots.en
dc.formattextcs
dc.format.extent197276-197286cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationIEEE Access. 2020, vol. 8, issue 1, p. 197276-197286.en
dc.identifier.doi10.1109/ACCESS.2020.3034665cs
dc.identifier.issn2169-3536cs
dc.identifier.orcid0000-0001-5286-9574cs
dc.identifier.orcid0000-0002-2430-1815cs
dc.identifier.other165781cs
dc.identifier.researcheridDZG-2188-2022cs
dc.identifier.researcheridG-4209-2017cs
dc.identifier.scopus9333762000cs
dc.identifier.scopus21834721500cs
dc.identifier.urihttp://hdl.handle.net/11012/195635
dc.language.isoencs
dc.publisherIEEEcs
dc.relation.ispartofIEEE Accesscs
dc.relation.urihttps://ieeexplore.ieee.org/document/9244145cs
dc.rightsCreative Commons Attribution 4.0 Internationalcs
dc.rights.accessopenAccesscs
dc.rights.sherpahttp://www.sherpa.ac.uk/romeo/issn/2169-3536/cs
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/cs
dc.subjectAnalogue binary memoryen
dc.subjectbifurcation diagramen
dc.subjectelectronic tuningen
dc.subjectchaosen
dc.subjectLyapunov exponenten
dc.subjectpiecewise-linear (PWL) resistorsen
dc.subjectstrange attractoren
dc.titleBinary Memory Implemented by Using Variable Gain Amplifiers With Multipliersen
dc.type.driverarticleen
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
sync.item.dbidVAV-165781en
sync.item.dbtypeVAVen
sync.item.insts2025.02.03 15:41:35en
sync.item.modts2025.01.17 16:34:59en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav radioelektronikycs
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