Lattice-based Multisignature Optimization for RAM Constrained Devices

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dc.contributor.authorRicci, Saracs
dc.contributor.authorShapoval, Vladyslavcs
dc.contributor.authorDzurenda, Petrcs
dc.contributor.authorRoenne, Petercs
dc.contributor.authorOupicky, Jancs
dc.contributor.authorMalina, Lukášcs
dc.date.accessioned2025-02-18T11:36:14Z
dc.date.available2025-02-18T11:36:14Z
dc.date.issued2024-07-30cs
dc.description.abstractIn the era of growing threats posed by the development of quantum computers, ensuring the security of electronic services has become fundamental. The ongoing standardization process led by the National Institute of Standards and Technology (NIST) emphasizes the necessity for quantum-resistant security measures. However, the implementation of Post-Quantum Cryptographic (PQC) schemes, including advanced schemes such as threshold signatures, faces challenges due to their large key sizes and high computational complexity, particularly on constrained devices. This paper introduces two microcontroller-tailored optimization approaches, focusing on enhancing the DS2 threshold signature scheme. These optimizations aim to reduce memory consumption while maintaining security strength, specifically enabling the implementation of DS2 on microcontrollers with only 192 KB of RAM. Experimental results and security analysis demonstrate the efficacy and practicality of our solution, facilitating the deployment of DS2 threshold signatures on resource-constrained microcontrollers.en
dc.formattextcs
dc.format.extent1-10cs
dc.format.mimetypeapplication/pdfcs
dc.identifier.citationARES '24: Proceedings of the 19th International Conference on Availability, Reliability and Security. 2024, p. 1-10.en
dc.identifier.doi10.1145/3664476.3670461cs
dc.identifier.isbn979-8-4007-1718-5cs
dc.identifier.orcid0000-0003-0842-4951cs
dc.identifier.orcid0000-0002-4366-3950cs
dc.identifier.orcid0000-0002-7208-2514cs
dc.identifier.other189220cs
dc.identifier.researcheridR-6057-2018cs
dc.identifier.researcheridAAC-8713-2019cs
dc.identifier.researcheridE-2174-2018cs
dc.identifier.scopus57126826900cs
dc.identifier.scopus56418733600cs
dc.identifier.scopus49863792100cs
dc.identifier.urihttps://hdl.handle.net/11012/250056
dc.language.isoencs
dc.publisherAssociation for Computing Machinerycs
dc.relation.ispartofARES '24: Proceedings of the 19th International Conference on Availability, Reliability and Securitycs
dc.relation.urihttps://dl.acm.org/doi/10.1145/3664476.3670461cs
dc.rightsCreative Commons Attribution 4.0 Internationalcs
dc.rights.accessopenAccesscs
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/cs
dc.subjectLattice-based cryptographyen
dc.subjectDilithiumen
dc.subjectthreshold signatureen
dc.subjectmicrocontrolleren
dc.subjectmemory optimizationen
dc.subjectrandom access memoryen
dc.subjectRAMen
dc.titleLattice-based Multisignature Optimization for RAM Constrained Devicesen
dc.type.driverconferenceObjecten
dc.type.statusPeer-revieweden
dc.type.versionpublishedVersionen
eprints.grantNumberinfo:eu-repo/grantAgreement/MV0/VJ/VJ03030014cs
sync.item.dbidVAV-189220en
sync.item.dbtypeVAVen
sync.item.insts2025.02.18 12:36:13en
sync.item.modts2025.02.13 15:32:06en
thesis.grantorVysoké učení technické v Brně. Fakulta elektrotechniky a komunikačních technologií. Ústav telekomunikacícs
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