VHDL Model of Electronic-Lock System
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Date
Authors
Vlcek, K.
Bannister, B. R.
Miklik, D.
Bell, I. M.
Bartsch, E.
Noga, J.
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Mark
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Společnost pro radioelektronické inženýrství
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Abstract
The paper describes the design of an electronic-lock system which was completed as part of the Basic VHDL course in the Department of Control and Measurement Faculty of Electrical Engineering and Informatics, Technical University of Ostrava, Czech Republic in co-operation with the Department if Electronic Engineering, University of Hull, Great Britain in the frame of TEMPUS project no. S_JEP/09468-95.
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Citation
Radioengineering. 2000, vol. 9, č. 1, s. 4-8. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2000/00_01_04_08.pdf
http://www.radioeng.cz/fulltexts/2000/00_01_04_08.pdf
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Peer-reviewed
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en
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Except where otherwised noted, this item's license is described as Creative Commons Attribution 3.0 Unported License