VHDL Model of Electronic-Lock System

Thumbnail Image
Files
00_01_04_08.pdf(1.87 MB)
Date
2000-04
Authors
ORCID
Advisor
Referee
Mark
Journal Title
Journal ISSN
Volume Title
Publisher
Společnost pro radioelektronické inženýrství
Abstract
The paper describes the design of an electronic-lock system which was completed as part of the Basic VHDL course in the Department of Control and Measurement Faculty of Electrical Engineering and Informatics, Technical University of Ostrava, Czech Republic in co-operation with the Department if Electronic Engineering, University of Hull, Great Britain in the frame of TEMPUS project no. S_JEP/09468-95.
Description
Keywords
system design, finite state machine, behavioural VHDL modelling, FPGA implementation
Citation
Radioengineering. 2000, vol. 9, č. 1, s. 4-8. ISSN 1210-2512
http://www.radioeng.cz/fulltexts/2000/00_01_04_08.pdf
Document type
Peer-reviewed
Document version
Published version
Date of access to the full text
Language of document
en
Study field
Comittee
Date of acceptance
Defence
Result of defence
Document licence
Creative Commons Attribution 3.0 Unported License
http://creativecommons.org/licenses/by/3.0/
DOI
URI
http://hdl.handle.net/11012/58215
Collections
2000/1
Citace PRO