Saving area and power consumption in 65 nm digital standard cell library

Král, Vojtěch

Saving area and power consumption in 65 nm digital standard cell library

but.event.date	26.04.2022	cs
but.event.title	STUDENT EEICT 2022	cs
dc.contributor.author	Král, Vojtěch
dc.date.accessioned	2023-04-25T10:17:07Z
dc.date.available	2023-04-25T10:17:07Z
dc.date.issued	2022	cs
dc.description.abstract	This study aims to investigate multi-bit pulsed latches in comparison with multi-bit flip flops as one of the low-power solutions in 65 nm technology process. Topologies of pulse generators and multi-bit pulsed latches were investigated to find out which can be more suitable. The pulse generator was chosen because of its low power and a small area in comparison with other options. The pulse generator is made of a simple AND logical gate and a double-stacked inverter. The pulsed latch was also chosen because of its low power, small area, and reliability of the circuit. The chosen topology is modified PPCLA. Simulations of the chosen topology had shown that multi-bit flip flops could be replaced with more effective multi-bit pulsed latches.	en
dc.format	text	cs
dc.format.extent	190-193	cs
dc.format.mimetype	application/pdf	en
dc.identifier.citation	Proceedings I of the 28st Conference STUDENT EEICT 2022: General papers. s. 190-193. ISBN 978-80-214-6029-4	cs
dc.identifier.isbn	978-80-214-6029-4
dc.identifier.uri	http://hdl.handle.net/11012/209324
dc.language.iso	en	cs
dc.publisher	Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií	cs
dc.relation.ispartof	Proceedings I of the 28st Conference STUDENT EEICT 2022: General papers	en
dc.relation.uri	https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni	cs
dc.rights	© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií	cs
dc.rights.access	openAccess	en
dc.subject	digital standard library	en
dc.subject	integrated circuits	en
dc.subject	chip development	en
dc.subject	low power methods	en
dc.subject	pulse generator	en
dc.subject	multi-bit pulsed latch	en
dc.title	Saving area and power consumption in 65 nm digital standard cell library	en
dc.type.driver	conferenceObject	en
dc.type.status	Peer-reviewed	en
dc.type.version	publishedVersion	en
eprints.affiliatedInstitution.department	Fakulta elektrotechniky a komunikačních technologií	cs

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