Saving area and power consumption in 65 nm digital standard cell library
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Date
2022
Authors
Král, Vojtěch
ORCID
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Referee
Mark
Journal Title
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Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií
Abstract
This study aims to investigate multi-bit pulsed latches in comparison with multi-bit flip flops as one of the low-power solutions in 65 nm technology process. Topologies of pulse generators and multi-bit pulsed latches were investigated to find out which can be more suitable. The pulse generator was chosen because of its low power and a small area in comparison with other options. The pulse generator is made of a simple AND logical gate and a double-stacked inverter. The pulsed latch was also chosen because of its low power, small area, and reliability of the circuit. The chosen topology is modified PPCLA. Simulations of the chosen topology had shown that multi-bit flip flops could be replaced with more effective multi-bit pulsed latches.
Description
Citation
Proceedings I of the 28st Conference STUDENT EEICT 2022: General papers. s. 190-193. ISBN 978-80-214-6029-4
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
https://conf.feec.vutbr.cz/eeict/index/pages/view/ke_stazeni
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Peer-reviewed
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en
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© Vysoké učení technické v Brně, Fakulta elektrotechniky a komunikačních technologií